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clock generator pll with integrated vco data sheet adf4360-9 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2008C2012 analog devices, inc. all rights reserved. features primary output frequency range: 65 mhz to 400 mhz auxiliary divider from 2 to 31, output from 1.1 mhz to 200 mhz 3.0 v to 3.6 v power supply 1.8 v logic compatibility integer-n synthesizer programmable output power level 3-wire serial interface digital lock detect software power-down mode applications system clock generation test equipment wireless lans catv equipment general description the adf4360-9 is an integrated integer-n synthesizer and voltage-controlled oscillator (vco). external inductors set the adf4360-9 center frequency. this allows a vco frequency range of between 65 mhz and 400 mhz. an additional divider stage allows division of the vco signal. the cmos level output is equivalent to the vco signal divided by the integer value between 2 and 31. this divided signal can be further divided by 2, if desired. control of all the on-chip registers is through a simple 3-wire interface. the device operates with a power supply ranging from 3.0 v to 3.6 v and can be powered down when not in use. functional block diagram 14-bit r counter a v dd clk data v tune c n c c rf out a rf out b ld cp v vco l1 divout l2 le dv dd r set lock detect multiplexer mute charge pump phase comparator 24-bit data register adf4360-9 13-bit b counter n = b vco core divide-by-a (2 to 31) divide-by-2 output stage 24-bit function latch ref in agnd dgnd cpgnd 07139-001 figure 1.
adf4360-9 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings............................................................ 6 transistor count........................................................................... 6 esd caution.................................................................................. 6 pin configuration and function descriptions............................. 7 typical performance characteristics ............................................. 8 circuit description......................................................................... 10 reference input section............................................................. 10 n counter.................................................................................... 10 r counter .................................................................................... 10 pfd and charge pump.............................................................. 10 lock detect ................................................................................. 10 input shift register .................................................................... 10 vco ............................................................................................. 11 output stage................................................................................ 12 divout stage............................................................................ 12 latch structure ........................................................................... 13 power-up..................................................................................... 17 control latch .............................................................................. 18 n counter latch......................................................................... 19 r counter latch ......................................................................... 19 applications..................................................................................... 20 choosing the correct inductance value................................. 20 encode clock for adc.............................................................. 20 gsm test clock .......................................................................... 21 interfacing ................................................................................... 22 pcb design guidelines for chip scale package .................... 22 output matching ........................................................................ 23 outline dimensions ....................................................................... 24 ordering guide .......................................................................... 24 revision history 2/12rev. a to rev. b added epad note............................................................................ 7 updated outline dimensions ....................................................... 24 changes to ordering guide .......................................................... 24 3/08rev. 0 to rev. a changes to table 1 ........................................................................... 3 changes to figure 23...................................................................... 14 changes to output matching section.......................................... 23 1/08revision 0: initial version
data sheet adf4360-9 rev. b | page 3 of 24 specifications av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; t a = t min to t max , unless otherwise noted. 1 table 1. parameter b version unit conditions/comments ref in characteristics ref in input frequency 10/250 mhz min/mhz max for f < 10 mhz, use a dc-coupled, cmos-compatible square wave, slew rate > 21 v/s ref in input sensitivity 0.7/av dd v p-p min/v p-p max ac-coupled 0 to av dd v max cmos-compatible ref in input capacitance 5.0 pf max ref in input current 60 a max phase detector phase detector frequency 2 8 mhz max charge pump i cp sink/source 3 with r set = 4.7 k high value 2.5 ma typ low value 0.312 ma typ r set range 2.7/10 k min/k max i cp three-state leakage current 0.2 na typ sink and source current matching 2 % typ 1.25 v v cp 2.5 v i cp vs. v cp 1.5 % typ 1.25 v v cp 2.5 v i cp vs. temperature 2 % typ v cp = 2.0 v logic inputs input high voltage, v inh 1.5 v min input low voltage, v inl 0.6 v max input current, i inh /i inl 1 a max input capacitance, c in 3.0 pf max logic outputs output high voltage, v oh dv dd ? 0.4 v min cmos output chosen output high current, i oh 500 a max output low voltage, v ol 0.4 v max i ol = 500 a power supplies av dd 3.0/3.6 v min/v max dv dd av dd v vco av dd ai dd 4 5 ma typ di dd 4 2.5 ma typ i vco 4 , 5 12.0 ma typ i core = 5 ma i rfout 4 3.5 to 11.0 ma typ rf output stage is programmable low power sleep mode 4 7 a typ rf output characteristics 5 maximum vco output frequency 400 mhz i core = 5 ma; depending on l1 and l2; see the choosing the correct inductance value section minimum vco output frequency 65 mhz vco output frequency 90/108 mhz min/mhz max l1, l2 = 270 nh; see the choosing the correct inductance value section for other frequency values vco frequency range 1.2 ratio f max /f min vco sensitivity 2 mhz/v typ l1, l2 = 270 nh; see the choosing the correct inductance value section for other sensitivity values lock time 6 400 s typ to within 10 hz of final frequency
adf4360-9 data sheet rev. b | page 4 of 24 parameter b version unit conditions/comments frequency pushing (open loop) 0.24 mhz/v typ frequency pulling (open loop) 10 hz typ into 2.00 vswr load harmonic content (second) ?16 dbc typ harmonic content (third) ?21 dbc typ output power 5 , 7 ?9/0 dbm typ using tuned load, programmable in 3 db steps; see figure 35 output power 5 , 8 ?14/?9 dbm typ using 50 resistors to v vco , programmable in 3 db steps; see figure 33 output power variation 3 db typ vco tuning range 1.25/2.5 v min/v max vco noise characteristics vco phase noise performance 9 ,10 ?91 dbc/hz typ @ 10 khz offset from carrier ?117 dbc/hz typ @ 100 khz offset from carrier ?139 dbc/hz typ @ 1 mhz offset from carrier ?140 dbc/hz typ @ 3 mhz offset from carrier ?147 dbc/hz typ @ 10 mhz offset from carrier normalized in-band phase noise 10 , 11 ?218 dbc/hz typ in-band phase noise 10, 11 ?110 dbc/hz typ @ 1 khz offset from carrier rms integrated jitter 12 1.4 ps typ measured at rf out a spurious signals due to pfd frequency 13 ?75 dbc typ divout characteristics 12 integrated jitter performance (integrated from 100 hz to 1 ghz) vco frequency = 320 mhz to 380 mhz divout = 180 mhz 1.4 ps rms a = 2, a output selected divout = 95 mhz 1.4 ps rms a = 2, a/2 output selected divout = 80 mhz 1.4 ps rms a = 2, a/2 output selected divout = 52 mhz 1.4 ps rms a = 3, a/2 output selected (vco = 312 mhz, pfd = 1.6 mhz) divout = 45 mhz 1.4 ps rms a = 4, a/2 output selected divout = 10 mhz 1.6 ps rms a = 18, a/2 output selected (vco = 360 mhz, pfd = 1.6 mhz) divout duty cycle a output 1/a 100 % typ divide-by-a selected a/2 output 50 % typ divide-by-a/2 selected 1 operating temperature range is ?40c to +85c. 2 guaranteed by design. sample tested to ensure compliance. 3 i cp is internally modified to maintain constant loop gain over the frequency range. 4 t a = 25c; av dd = dv dd = v vco = 3.3 v. 5 unless otherwise stated , these characteristics are guaranteed for vco core power = 5 ma. l1, l2 = 270 nh, 470 resistors to g nd in parallel with l1, l2. 6 jumping from 90 mhz to 108 mhz. pfd frequency = 200 khz; loop bandwidth = 10 khz. 7 for more detail on using tuned loads, see the out section. put matching 8 using 50 resistors to v vco into a 50 load. 9 the noise of the vco is measured in open-loop conditions. l1, l2 = 56 nh. 10 the phase noise is me asured with the ev-adf4360-9eb 1 z evaluation board and the agilent e5052a signal source analyzer. 11 f refin = 10 mhz; f pfd = 1 mhz; n = 360; loop b/w = 40 khz. the normalized phase nois e floor is estimated by measuring the in-band phase noise at the output of the vco and subtracting 20logn (where n is the n divider value) and 10logf pfd . pn synth = pn tot ? 10logf pfd ? 20logn. 12 the jitter is measured with the ev-adf 4360-9eb1 z evaluation board and the agilent e5052a signal source analyzer. a low noise tcxo provides the ref in for the sy nthesizer, and the jitter is measured over the instruments jitter measurement bandwidth. f refin = 10 mhz; f pfd = 1 mhz; n = 360; loop bw = 40 khz, unless otherwise noted. 13 the spurious signals are meas ured with the ev-adf4360-9eb 1z ev aluation board and the agilent e5052a signal so urce analyzer. the spectrum analyzer provides the ref in for the synthesizer; f refin = 10 mhz @ 0 dbm. f refin = 10 mhz; f pfd = 1 mhz; n = 360; loop bw = 40 khz.
data sheet adf4360-9 rev. b | page 5 of 24 timing characteristics 1 av dd = dv dd = v vco = 3.3 v 10%; agnd = dgnd = 0 v; 1.8 v and 3 v logic levels used; t a = t min to t max , unless otherwise noted. table 2. parameter limit at t min to t max (b version) unit test conditions/comments t 1 20 ns min le setup time t 2 10 ns min data to clk setup time t 3 10 ns min data to clk hold time t 4 25 ns min clk high duration t 5 25 ns min clk low duration t 6 10 ns min clk to le setup time t 7 20 ns min le pulse width 1 refer to the section for the reco mmended power-up procedure for this device. power-up clk data le le db23 (msb) db22 db2 db1 (control bit c2) db0 (lsb) (control bit c1) t 1 t 2 t 3 t 7 t 6 t 4 t 5 07139-002 figure 2. timing diagram
adf4360-9 data sheet rev. b | page 6 of 24 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating av dd to gnd 1 ?0.3 v to +3.9 v av dd to dv dd ?0.3 v to +0.3 v v vco to gnd ?0.3 v to +3.9 v v vco to av dd ?0.3 v to +0.3 v digital input/output voltage to gnd ?0.3 v to v dd + 0.3 v analog input/output voltage to gnd ?0.3 v to v dd + 0.3 v ref in to gnd ?0.3 v to v dd + 0.3 v operating temperature range ?40c to + 85c storage temperature range ?65c to +150c maximum junction temperature 150c lfcsp ja thermal impedance paddle soldered 50c/w paddle not soldered 88c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 gnd = cpgnd = agnd = dgnd = 0 v. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <1 kv, and it is esd sensitive. proper precautions should be taken for handling and assembly. transistor count the transistor count is 12,543 (cmos) and 700 (bipolar). esd caution
data sheet adf4360-9 rev. b | page 7 of 24 pin configuration and fu nction descriptions pin 1 indicator 1 cpgnd 2 av dd 3 agnd 4 rf out a 5 rf out b 6v vco 15 dgnd 16 ref in 17 clk 18 data 14 c n 13 r set 7 v tune 8 agnd 9 l1 11 agnd 12 c c 10 l2 21 dv dd 22 agnd 23 ld 24 cp 20 divou t 19 le top view (not to scale) adf4360-9 07139-003 note the exposed p a ddle must be connected to a gnd. figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic description 1 cpgnd charge pump ground. this is the ground return path for the charge pump. 2 av dd analog power supply. this ranges from 3.0 v to 3.6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. av dd must have the same value as dv dd . 3, 8, 11, 22 agnd analog ground. this is the ground return path of the prescaler and vco. 4 rf out a vco output. the output level is programmable from 0 dbm to ?9 dbm. see the output matching section for a description of the various output stages. 5 rf out b vco complementary output. the output level is programmable from 0 dbm to ?9 dbm. see the output matching section for a description of the various output stages. 6 v vco power supply for the vco. this ranges from 3.0 v to 3. 6 v. decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. v vco must have the same value as av dd . 7 v tune control input to the vco. this voltage determines the output frequency and is derive d from filtering the cp output voltage. 9 l1 an external inductor to agnd should be connected to this pin to set the adf4360-9 output frequency. l1 and l2 need to be the same value. a 470 resi stor should be added in parallel to agnd. 10 l2 an external inductor to agnd should be connected to this pin to set the adf4360-9 output frequency. l1 and l2 need to be the same value. a 470 resi stor should be added in parallel to agnd. 12 c c internal compensation node. this pin must be decoupled to ground with a 10 nf capacitor. 13 r set connecting a resistor between this pin and cpgnd se ts the maximum charge pump output current for the synthesizer. the nominal voltage potential at the r set pin is 0.6 v. the relationship between i cp and r set is i cpmax = 11.75/ r set for example, r set = 4.7 k and i cpmax = 2.5 ma. 14 c n internal compensation node. this pin must be decoupled to v vco with a 10 f capacitor. 15 dgnd digital ground. 16 ref in reference input. this is a cmos in put with a nominal threshold of v dd /2 and a dc equivalent input resistance of 100 k (see figure 16 ). this input can be driven from a ttl or cmos crystal oscillator, or it can be ac-coupled. 17 clk serial clock input. this serial clock is used to clock in th e serial data to the registers. the data is latched into the 24-bit shift register on the clk rising edge. this input is a high impedance cmos input. 18 data serial data input. the serial data is loaded msb first with the two lsbs being the control bits. this input is a high impedance cmos input. 19 le load enable, cmos input. when le goes high, the data st ored in the shift registers is loaded into one of the four latches, and the relevant latch is selected using the control bits. 20 divout this output allows the user to select vco freque ncy divided by a or vco frequency divided by 2a. alternatively, the scaled rf, or the scaled reference freq uency, can be accessed externally through this output. 21 dv dd digital power supply. this ranges from 3.0 v to 3.6 v. de coupling capacitors to the digital ground plane should be placed as close as possible to this pin. dv dd must have the same value as av dd . 23 ld lock detect. the output on this pin is logic high to indicate that the part is in lock. logic low indicates loss of lock. 24 cp charge pump output. when enabled, this provides i cp to the external loop filter, which in turn drives the internal vco. ep exposed pad. the exposed pad must be connected to agnd.
adf4360-9 data sheet rev. b | page 8 of 24 typical performance characteristics ? 20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 1k 10k 100k 1m 10m 07139-004 phase noise (dbc/hz) frequency (hz) figure 4. open-loop vco phase noise at 218 mhz, l1, l2 = 56 nh ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 100 10k 100k 1k 10m 07139-005 phase noise (dbc/hz) frequency offset (hz) figure 5. vco phase noise, 360 mhz, 1 mhz pfd, 40 khz loop bandwidth, rms jitter = 1.4 ps ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 1k 100 10k 100k 1m 10m 07139-006 frequency offset (hz) figure 6. divout phase noise, 180 mhz, vco = 360 mhz, pfd frequency = 1 mhz, loop band width = 40 khz, jitter = 1.3 ps, divide-by-a selected, a = 2 ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 1k 100 10k 100k 1m 10m 07139-007 phase noise (dbc/hz) frequency (hz) figure 7. divout phase noise, 95 mhz, vco = 380 mhz, pfd frequency = 1 mhz, loop band width = 40 khz, jitter = 1.3 ps, divide-by-a/2 selected, a = 2 ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 1k 100 10k 100k 1m 10m 07139-008 frequency offset (hz) figure 8. divout phase noise, 80 mhz, vco = 320 mhz, pfd frequency = 1 mhz, loop band width = 40 khz, jitter = 1.3 ps, divide-by-a/2 selected, a = 2 100 1k 10k 100k 1m frequency offset (hz) ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 07139-009 figure 9. divout phase noise, 52 mhz, vco = 312 mhz, pfd frequency = 1.6 mhz, loop bandwidth = 40 khz, jitter = 1.4 ps, divide-by-a/2 selected, a = 3
data sheet adf4360-9 rev. b | page 9 of 24 ? 60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 ?150 ?160 phase noise (dbc/hz) 1k 100 10k 100k 1m 10m 07139-010 frequency offset (hz) figure 10. divout phase noise, 45 mhz, vco = 360 mhz, pfd frequency = 1.6 mhz, loop bandwidth = 60 khz, jitter = 1.4 ps, divide-by-a/2 selected, a = 2 ? 100 ?110 ?120 ?130 ?140 ?150 ?160 1k 10k 100k 1m 10m 07139-011 phase noise (dbc/hz) frequency offset (hz) +25c ?40c +85c figure 11. divout phase noise over temperature, 52 mhz, vco = 312 mhz, pfd frequency = 1 mhz, loop bandwidth = 60 khz, divide-by-a/2 selected, a = 3 07139-012 ch1 500mv m 2.00ns a ch1 20mv 1 c1 frequency: 180mhz c1 + duty: 45.32% figure 12. divout 180 mhz waveform, vco = 360 mhz, divide-by-a selected, a = 2, duty cycle = ~50% 07139-013 ch1 500mv m 2.00ns 1 a ch1 20mv c1 frequency: 90mhz c1 + duty: 28.98% c1 peak to peak: 1.55v figure 13. divout 90 mhz waveform, vco = 360 mhz, divide-by-a selected, a = 4, duty cycle = ~25% 07139-014 ch1 500mv m 5.00ns a ch1 920mv 1 c1 frequency: 36.01mhz c1 + duty: 13.13% c1 peak to peak 1.28v figure 14. divout 36 mhz waveform, vco = 360 mhz, divide-by-a selected, a = 10, duty cycle = ~10% 07139-015 ch1 500mv m 12.5ns a ch1 920mv 1 c1 frequency: 36mhz c1 + duty: 49.41% figure 15. divout 36 mhz waveform, vco = 360 mhz, divide-by-a/2 selected, a = 5, duty cycle = ~50%
adf4360-9 data sheet rev. b | page 10 of 24 circuit description reference input section the reference input stage is shown in figure 16 . sw1 and sw2 are normally closed switches, and sw3 is normally open. when power-down is initiated, sw3 is closed, and sw1 and sw2 are opened. this ensures that there is no loading of the ref in pin at power-down. 07139-016 buffer to r counter ref in 100k ? nc sw2 sw3 no nc sw1 power-down control figure 16. reference input stage n counter the cmos n counter allows a wide division ratio in the pll feedback counter. the counters are specified to work when the vco output is 400 mhz or less. to avoid confusion, this is referred to as the b counter. it makes it possible to generate output frequencies that are spaced only by the reference frequency divided by r. the vco frequency equation is f vco = b f refin / r where: f vco is the output frequency of the vco. b is the preset divide ratio of the binary 13-bit counter (3 to 8191). f refin is the external reference frequency oscillator. r counter the 14-bit r counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (pfd). division ratios from 1 to 16,383 are allowed. pfd and charge pump the pfd takes inputs from the r counter and n counter (n = b) and produces an output proportional to the phase and frequency difference between them. figure 17 is a simplified schematic. the pfd includes a programmable delay element that controls the width of the antibacklash pulse. this pulse ensures that there is no dead zone in the pfd transfer function and minimizes phase noise and reference spurs. two bits in the r counter latch, abp2 and abp1, control the width of the pulse (see figure 25 ). 07139-017 programmable delay u3 clr2 q2 d2 u2 clr1 q1 d1 charge pump down up hi hi u1 abp1 abp2 r divider n divider cp output r divider n divider cp cpgnd v p figure 17. pfd simplified schematic and timing (in lock) lock detect the ld pin outputs a lock detect signal. digital lock detect is active high. when lock detect precision (ldp) in the r counter latch is set to 0, digital lock detect is set high when the phase error on three consecutive phase detector cycles is <15 ns. when ldp is set to 1, five consecutive cycles of <15 ns phase error are required to set the lock detect. it stays set high until a phase error of >25 ns is detected on any subsequent pd cycle. input shift register the digital section of the adf4360 family includes a 24-bit input shift register, a 14-bit r counter, and an 18-bit n counter, comprising a 5-bit a counter and a 13-bit b counter. data is clocked into the 24-bit shift register on each rising edge of clk. the data is clocked in msb first. data is transferred from the shift register to one of four latches on the rising edge of le. the destination latch is determined by the state of the two control bits (c2, c1) in the shift register. the two lsbs, db1 and db0, are shown in figure 2 .
data sheet adf4360-9 rev. b | page 11 of 24 the truth table for these bits is shown in table 5 . figure 22 shows a summary of how the latches are programmed. note that the test modes latch is used for factory testing and should not be programmed by the user. table 5. c2 and c1 truth table control bits c2 c1 data latch 0 0 control 0 1 r counter 1 0 n counter (b) 1 1 test modes vco the vco core in the adf4360 family uses eight overlapping bands, as shown in figure 18 , to allow a wide frequency range to be covered without a large vco sensitivity (k v ) and resultant poor phase noise and spurious performance. the correct band is chosen automatically by the band select logic at power-up or whenever the n counter latch is updated. it is important that the correct write sequence be followed at power-up. the correct write sequence is as follows: 1. r counter latch 2. control latch 3. n counter latch during band selection, which takes five pfd cycles, the vco v tune is disconnected from the output of the loop filter and connected to an internal reference voltage. 0 1.0 0.5 2.5 2.0 1.5 3.5 3.0 80 85 90 100 95 105 115 110 frequency (mhz) v tune (v) 07139-019 figure 18. v tune , adf4360-9, l1 and l2 = 270 nh vs. frequency the r counter output is used as the clock for the band select logic and should not exceed 1 mhz. a programmable divider is provided at the r counter input to allow division by 1, 2, 4, or 8 and is controlled by the bsc1 bit and the bsc2 bit in the r counter latch. where the required pfd frequency exceeds 1 mhz, the divide ratio should be set to allow enough time for correct band selection. for many applications, it is usually best to set this to 8. after band selection, normal pll action resumes. the value of k v is determined by the value of the inductors used (see the choosing the correct inductance value section). the adf4360 family contains linearization circuitry to minimize any variation of the product of i cp and k v . the operating current in the vco core is programmable in four steps: 2.5 ma, 5 ma, 7.5 ma, and 10 ma. this is controlled by the pc1 bit and the pc2 bit in the control latch. it is strongly recommended that only the 5 ma setting be used. however, in applications requiring a low vco frequency, the high temperature coefficient of some inductors may lead to the vco tuning voltage varying as temperature changes. the 7.5 ma vco core power setting shows less tuning voltage variation over temperature in these applications and can be used, provided that 240 resistors are used in parallel with pin 9 and pin 10, instead of the default 470 .
adf4360-9 data sheet rev. b | page 12 of 24 output stage the rf out a and rf out b pins of the adf4360 family are connected to the collectors of an npn differential pair driven by buffered outputs of the vco, as shown in figure 19 . to allow the user to optimize the power dissipation vs. the output power requirements, the tail current of the differential pair is programmable via bit pl1 and bit pl2 in the control latch. four current levels can be set: 3.5 ma, 5 ma, 7.5 ma, and 11 ma. these levels give output power levels of ?9 dbm, ?6 dbm, ?3 dbm, and 0 dbm, respectively, using the correct shunt inductor to v dd and ac coupling into a 50 load. alternatively, both outputs can be combined in a 1 + 1:1 transformer or a 180 microstrip coupler (see the output matching section). another feature of the adf4360 family is that the supply current to the rf output stage is shut down until the part achieves lock, as measured by the digital lock detect circuitry. this is enabled by the mute-till-lock detect (mtld) bit in the control latch. vco rf out a rf out b buffer 07139-020 figure 19. rf output stage divout stage the output multiplexer on the adf4360 family allows the user to access various internal points on the chip. the state of divout is controlled by d3, d2, and d1 in the control latch. the full truth table is shown in figure 23 . figure 20 shows the divout section in block diagram form. r counter output n counter output a counter output dgnd control mux divout dv dd a counter/2 output 07139-018 figure 20. divout circuit the primary use of this pin is to derive the lower frequencies from the vco by programming various divider values to the auxiliary a divider. values ranging from 2 to 31 are possible. the duty cycle of this output is 1/a times 100%, with the logic high pulse width equal to the inverse of the vco frequency. that is, pulse width [seconds] = 1/ f vco (frequency [hz]) see figure 21 for a graphical description. by selecting the divide-by-2 function, this divided down frequency can in turn be divided by 2 again. this provides a 50% duty cycle in contrast to the a counter output, which may be more suitable for some applications (see figure 21 ). f vco f vco /a (a = 4) f vco /2a (a = 4) 07139-021 figure 21. divo ut waveforms
data sheet adf4360-9 rev. b | page 13 of 24 latch structure figure 22 shows the three on-chip latches for the adf4360-9. the two lsbs decide which latch is programmed. db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 cr d1 d2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 d3 control bits divout control current setting 2 current setting 1 core power level output power level control latch db21 db22 db23 power- down 2 power- down 1 counter reset mute-till- ld reserved reserved cp gain cp three- state phase detector polarity pd2 rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1 a2a3 a4 a5 b1b2 b3b4b5b6b7b8b9 b10 b11 b12 b13 rsv control bits 5-bit divout 13-bit b counter n counter latch db21 db22 db23 cp gain reserved reserved reserved cpg rsv rsv db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1 r2r3 r4 r5 r7r8 r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 control bits anti- backlash pulse width 14-bit reference counter band select clock r counter latch db21 db22 db23 reserved reserved test mode bit lock detect precision bsc2 rsv rsv 07139-034 figure 22. latch structure
adf4360-9 data sheet rev. b | page 14 of 24 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (0) pc1 pc2 crd1d2 pdp cp cpg mtld pl1 pl2 cpi1 cpi2 cpi3 cpi4 cpi5 cpi6 pd1 d3 control bits divout control current setting 2 current setting 1 core power level output power level db21 db22 db23 power- down 2 power- down 1 counter reset mute-till- ld reserved reserved cp gain cp three- state phase detector polarity pd2 rsv rsv cr 0 1 counter operation normal r, a, b counters held in reset pc2 0 0 1 0 core power level 2.5ma 5ma (recommended) 7.5ma pc1 0 1 1 1 10ma cp 0 1 charge pump output normal three-state pdp 0 1 phase detector polarity negative positive cpg 0 1 cp gain current setting 1 current setting 2 mtld 0 1 mute-til-lock detect disabled enabled d3 d2 d1 muxout dv dd 000 001 010 011 100 101 110 111 digital lock detect (active high) n divider output dv dd r divider output a cntr/2 out a cntr out dgnd ce pin pd2 pd1 mode 0 x x asynchronous power-down 1 x 0 normal operation 1 0 1 asynchronous power-down 1 1 1 synchronous power-down cpi6 cpi5 cpi4 i cp (ma) cpi3 cpi2 cpi1 4.7k ? 0.31 0.62 0.93 1.25 1.56 1.87 2.18 2.50 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 pl2 pl1 output power level current using tuned load ?9dbm ?6dbm ?3dbm 0dbm using 50 ? to v vco ?19dbm ?15dbm ?12dbm ?9dbm 0 0 1 1 0 1 0 1 3.5ma 5.0ma 7.5ma 11.0ma 07139-022 these bits are not used by the device and are don't care bits. figure 23. control latch
data sheet adf4360-9 rev. b | page 15 of 24 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (1) c1 (0) a1a2a3a4a5 b1b2b3b4b5b6b7b8b9 b10 b11 b12 b13 rsv control bits 5-bit divout 13-bit b counter db21 db22 db23 cp gain reserved reserved cpg rsv rsv b13 0 0 0 0 . . . 1 1 1 1 b12 0 0 0 0 . . . 1 1 1 1 b11 0 0 0 0 . . . 1 1 1 1 ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ b3 0 0 1 0 . . . 1 1 1 1 b2 0 0 1 1 . . . 0 0 1 1 b1 0 1 1 0 . . . 0 1 0 1 b counter divide ratio not allowed not allowed 3 not allowed . . . 8188 8189 8190 8191 a5 0 0 0 0 . . . 1 1 1 1 a4 0 0 0 0 . . . 1 1 1 1 ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ ............ a2 0 0 1 1 . . . 0 0 1 1 a1 0 1 1 0 . . . 0 1 0 1 output divide ratio not allowed not allowed 3 2 . . . 28 29 30 31 cp gain operation 0 charge pump current setting 1 is permanently used 1 charge pump current setting 2 is permanently used 07139-023 these bits are not used by the device and are don't care bits. this bit is not used by the device and is a don't care bit. figure 24. n counter latch
adf4360-9 data sheet rev. b | page 16 of 24 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 c2 (0) c1 (1) r1r2r3 r4 r5 r7r8r9 r10 r11 r12 r13 r14 abp1 abp2 ldp tmb bsc1 r6 control bits band select clock anti- backlash pulse width 14-bit reference counter db21 db22 db23 lock detect precision test mode bit reserved reserved bsc2 rsv rsv test mode bit should be set to 0 for normal operation. r14 r13 r12 r3 r2 r1 divide ratio .......... 0 00 0 00 0 00 0 00 0 01 1 .......... 0 1 0 2 .......... 0 1 1 3 .......... 1 0 0 4 .......... . .. . .. . .. . .. . .......... . . . . .......... . . . . .......... 1 11 1 11 1 11 1 11 1 0 0 16380 .......... 1 0 1 16381 .......... 1 1 0 16382 .......... 1 1 1 16383 these bits are not used by the device and are don't care bits. 07139-024 ldp lock detect precision 0 three consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 1 five consecutive cycles of phase delay less than 15ns must occur before lock detect is set. abp2 abp1 antibacklash pulse width 00 3.0ns 01 1.3ns 10 6.0ns 11 3.0ns bsc2 bsc1 band select clock divider 00 1 01 2 10 4 11 8 figure 25. r counter latch
data sheet adf4360-9 rev. b | page 17 of 24 power-up power-up sequence the correct programming sequence for the adf4360-9 after power-up is as follows: 1. r counter latch 2. control latch 3. n counter latch initial power-up initial power-up refers to programming the part after the application of voltage to the av dd , dv dd , and v vco pins. on initial power-up, an interval is required between programming the control latch and programming the n counter latch. this interval is necessary to allow the transient behavior of the adf4360-9 during initial power-up to settle. during initial power-up, a write to the control latch powers up the part, and the bias currents of the vco begin to settle. if these currents have not settled to within 10% of their steady- state value, and if the n counter latch is then programmed, the vco may not oscillate at the desired frequency, which does not allow the band select logic to choose the correct frequency band, and the adf4360-9 may not achieve lock. if the recommended interval is inserted, and the n counter latch is programmed, the band select logic can choose the correct frequency band, and the part locks to the correct frequency. the duration of this interval is affected by the value of the capacitor on the c n pin (pin 14). this capacitor is used to reduce the close-in noise of the adf4360-9 vco. the recommended value of this capacitor is 10 f. using this value requires an interval of 15 ms between the latching in of the control latch bits and latching in of the n counter latch bits. if a shorter delay is required, the capacitor can be reduced. a slight phase noise penalty is incurred by this change, which is further explained in table 6 . table 6. c n capacitance vs. interval and phase noise open-loop phase noise @ 10 khz offset c n value recommended interval between control latch and n counter latch l1 and l2 = 18.0 nh l1 and l2 = 110.0 nh l1 and l2 = 560.0 nh 10 f 15 ms ?100 dbc/hz ?97 dbc/hz ?99 dbc/hz 440 nf 600 s ?99 dbc/hz ?96 dbc/hz ?98 dbc/hz clk power-up data le r counter latch data control latch data n counter latch data required interval control latch write to n counter latch write 07139-033 figure 26. power-up timing
adf4360-9 data sheet rev. b | page 18 of 24 software power-up/power-down if the part is powered down via the software (using the control latch) and powered up again without any change to the n counter latch during power-down, the part locks at the correct frequency because the part is already in the correct frequency band. the lock time depends on the value of capacitance on the c n pin, which is <15 ms for 10 f capacitance. the smaller capacitance of 440 nf on this pin enables lock times of <600 s. the n counter value cannot be changed while the part is in power-down because the part may not lock to the correct frequency on power-up. if it is updated, the correct program- ming sequence for the part after power-up is to the r counter latch, followed by the control latch, and finally the n counter latch, with the required interval between the control latch and n counter latch, as described in the initial power-up section. control latch with (c2, c1) = (0, 0), the control latch is programmed. figure 23 shows the input data format for programming the control latch. power-down db21 (pd2) and db20 (pd1) provide programmable power- down modes. in the programmed asynchronous power-down, the device powers down immediately after latching a 1 into bit pd1, with the condition that pd2 is loaded with a 0. in the programmed synchronous power-down, the device power-down is gated by the charge pump to prevent unwanted frequency jumps. once the power-down is enabled by writing a 1 into bit pd1 (on the condition that a 1 is also loaded in pd2), the device goes into power-down on the second rising edge of the r counter output, after le goes high. when a power-down is activated (either synchronous or asynchronous mode), the following events occur: ? all active dc current paths are removed. ? the r, n, and timeout counters are forced to their load state conditions. ? the charge pump is forced into three-state mode. ? the digital lock detect circuitry is reset. ? the rf outputs are debiased to a high impedance state. ? the reference input buffer circuitry is disabled. ? the input register remains active and capable of loading and latching data. charge pump currents cpi3, cpi2, and cpi1 in the adf4360 family determine current setting 1. cpi6, cpi5, and cpi4 determine current setting 2 (see the truth table in figure 23 ). output power level bit pl1 and bit pl2 set the output power level of the vco (see the truth table in figure 23 ). mute-till-lock detect db11 of the control latch in the adf4360 family is the mute- till-lock detect bit. this function, when enabled, ensures that the rf outputs are not switched on until the pll is locked. cp gain db10 of the control latch in the adf4360 family is the charge pump gain bit. when it is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. charge pump three-state this bit (db9) puts the charge pump into three-state mode when programmed to a 1. for normal operation, it should be set to 0. phase detector polarity the pdp bit in the adf4360 family sets the phase detector polarity. the positive setting enabled by programming a 1 is used when using the on-chip vco with a passive loop filter or with an active noninverting filter. it can also be set to 0, which is required if an active inverting loop filter is used. divout control the on-chip multiplexer is controlled by d3, d2, and d1 (see the truth table in figure 23 ). counter reset db4 is the counter reset bit for the adf4360 family. when this is 1, the r counter and the a, b counters are reset. for normal operation, this bit should be 0. core power level pc1 and pc2 set the power level in the vco core. the recommended setting is 5 ma. the 7.5 ma setting is permissible in some applications (see the truth table in figure 23 ).
data sheet adf4360-9 rev. b | page 19 of 24 n counter latch figure 24 shows the input data format for programming the n counter latch. 5-bit divider a5 to a1 program the output divider. the divide range is 2 (00010) to 31 (11111). if unused, this divider should be set to 0. the output or the output divided by 2 is available at the divout pin. reserved bits db23, db22, and db7 are spare bits and are designated as reserved. they should be programmed to 0. b counter latch b13 to b1 program the b counter. the divide range is 3 (00 0011) to 8191 (11 111). overall divide range the overall vco feedback divide range is defined by b. cp gain db21 of the n counter latch in the adf4360 family is the charge pump gain bit. when it is programmed to 1, current setting 2 is used. when programmed to 0, current setting 1 is used. this bit can also be programmed through db10 of the control latch. the bit always reflects the latest value written to it, whether this is through the control latch or the n counter latch. r counter latch with (c2, c1) = (0, 1), the r counter latch is programmed. figure 25 shows the input data format for programming the r counter latch. r counter r1 to r14 set the counter divide ratio. the divide range is 1 (00 001) to 16,383 (111 111). antibacklash pulse width db16 and db17 set the antibacklash pulse width. lock detect precision db18 is the lock detect precision bit. this bit sets the number of reference cycles with <15 ns phase error for entering the locked state. with ldp at 1, five cycles are taken; with ldp at 0, three cycles are taken. test mode bit db19 is the test mode bit (tmb) and should be set to 0. with tmb = 0, the contents of the test mode latch are ignored and normal operation occurs, as determined by the contents of the control latch, r counter latch, and n counter latch. note that test modes are for factory testing only and should not be programmed by the user. band select clock these bits (db20 and db21) set a divider for the band select logic clock input. the output of the r counter is, by default, the value used to clock the band select logic; if this value is too high (>1 mhz), a divider can be switched on to divide the r counter output to a smaller value (see figure 25 ). a value of 8 is recommended. reserved bits db23 to db22 are spare bits that are designated as reserved. they should be programmed to 0.
adf4360-9 data sheet rev. b | page 20 of 24 applications choosing the correct inductance value the adf4360-9 can be used at many different frequencies simply by choosing the external inductors to give the correct output frequency. figure 27 shows a graph of both minimum and maximum frequency vs. the external inductor value. the correct inductor should cover the maximum and minimum frequencies desired. the inductors used are 0603 cs or 0805 cs type from coilcraft. to reduce mutual coupling, the inductors should be placed at right angles to one another. the lowest center frequency of oscillation possible is approximately 65 mhz, which is achieved using 560 nh inductors. this relationship can be expressed by () ext o l f + = nh0.9pf9.3 2 1 where: f o is the center frequency. l ext is the external inductance. 0 150 50 100 350 250 300 200 450 400 0 100 200 300 400 600 500 inductance (nh) frequency (mhz) 07139-025 figure 27. output center frequency vs. external inductor value the approximate value of capacitance at the midpoint of the center band of the vco is 9.3 pf, and the approximate value of internal inductance due to the bond wires is 0.9 nh. the vco sensitivity is a measure of the frequency change vs. the tuning voltage. it is a very important parameter for the low-pass filter. figure 28 shows a graph of the tuning sensitivity (in mhz/v) vs. the inductance (nh). it can be seen that as the inductance increases, the sensitivity decreases. this relationship can be derived from the previous equation; that is, because the inductance increased, the change in capacitance from the varactor has less of an effect on the frequency. 0 4 2 10 8 6 12 0 100 200 300 400 600 500 inductance (nh) sensitivity (mhz/v) 07139-026 figure 28. tuning sensitivity vs. inductance encode clock for adc analog-to-digital converters (adcs) require a sampling clock for their operation. generally, this is provided by tcxo or vcxos, which can be large and expensive. the frequency range is usually quite limited. an alternative solution is the adf4360-9, which can be used to generate a cmos clock signal suitable for use in all but the most demanding converter applications. figure 29 shows an adf4360-9 with a vco frequency of 320 mhz and a divout frequency of 80 mhz. because a 50% duty cycle is preferred by most sampling clock circuitry, the a/ mode is selected. therefore, a is programmed to 2, giving an overall divide value of 4. the 2 to z ter of <1.5 ps, which is more than adequate for the application. ad9215-80 is a 10-bit, 80 msps adc that requires an encode clock jitter of 6 ps or less. the adf4360-9 takes a 10 mhz tcxo frequency and divides this 1 mhz; therefore, r = 10 is programmed and n = 320 is programmed to achieve a vco frequency of 320 mhz. the resultant 80 mh cmos signal has a jit tcxo 10mhz adf4360-9 80mhz 470? 470 ? 21nh 21nh lpf signal generator hc-adc- evala-sc usb spi pc encode clock ad9215-80 a in 07139-036 figure 29. the adf4360-9 used as an encode clock for an adc
data sheet adf4360-9 rev. b | page 21 of 24 gsm test clock figure 30 shows the adf4360-9 used to generate three different frequencies at divout. the frequencies required are 45 mhz, 80 mhz, and 95 mhz. this is achieved by generating 360 mhz, 320 mhz, and 380 mhz and programming the correct a divider ratio. because a 50% duty cycle is required, the a/2 divout mode is selected. this means that a values of 4, 2, and 2 are selected, respectively, for each of the output frequencies previously mentioned. the low-pass filter was designed using adisimpll? for a channel spacing of 1 mhz and an open-loop bandwidth of 40 khz. larger pfd frequencies can be used to reduce in-band noise and, therefore, rms jitter. however, for the purposes of this example, 1 mhz is used. the measured rms jitter from this circuit at each frequency is less than 1.5 ps. two 21 nh inductors are required for the specified frequency range. the reference frequency is from a 20 mhz tcxo from fox; therefore, an r value of 20 is programmed. taking into account the high pfd frequency and its effect on the band select logic, the band select clock divider is enabled. in this case, a value of 8 is chosen. a very simple shunt resistor and dc-blocking capacitor complete the rf output stage. because these outputs are not used, they are terminated in 50 resistors. this is recommended for circuit stability. leaving the rf outputs open is not recommended. the cmos level output frequency is available at divout. if the frequency has to drive a low impedance load, a buffer is recommended. spi-compatible serial bus adf4360-9 v vco v vco fox 801be-160 20mhz v vco cpgnd agnd dgnd l1 l2 rf out b rf out a cp divout 1nf 150pf 21nh 470 ? 21nh 470 ? 56pf 2.2nf 51? 100pf 100pf 1nf1nf 10f 4.7k ? 5.6k ? 12k ? r set c c le data clk ref in c n v tune av dd dv dd ld 5 4 7 23 21 2 6 14 16 17 18 19 13 1 3 8 9 10 11 22 15 12 51? 51? 51? 51 ? v vdd loc k detect 07139-027 20 24 figure 30.gsm test clock
adf4360-9 data sheet rev. b | page 22 of 24 interfacing the adf4360 family has a simple spi-compatible serial interface for writing to the device. clk, data, and le control the data transfer. when le goes high, the 24 bits that are clocked into the appropriate register on each rising edge of clk are transferred to the appropriate latch. see figure 2 for the timing diagram and table 5 for the latch truth table. the maximum allowable serial clock rate is 20 mhz. this means that the maximum update rate possible is 833 khz, or one update every 1.2 s. this is more than adequate for systems that have typical lock times in hundreds of microseconds. aduc812 interface figure 31 shows the interface between the adf4360 family and the aduc812 microconverter?. because the aduc812 is based on an 8051 core, this interface can be used with any 8051-based microcontrollers. the microconverter is set up for spi master mode with cpha = 0. to initiate the operation, the i/o port driving le is brought low. each latch of the adf4360 family needs a 24-bit word, which is accomplished by writing three 8-bit bytes from the microconverter to the device. after the third byte is written, the le input should be brought high to complete the transfer. 07139-028 aduc812 adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi i/o ports figure 31. aduc812 to adf4360-x interface i/o port lines on the aduc812 are used to detect lock (muxout configured as lock detect and polled by the port input). when operating in the described mode, the maximum sclock rate of the aduc812 is 4 mhz. this means that the maximum rate at which the output frequency can be changed is 166 khz. adsp-21xx interface figure 32 shows the interface between the adf4360 family and the adsp-21xx digital signal processor. the adf4360 family needs a 24-bit serial word for each latch write. the easiest way to accomplish this using the adsp-21xx family is to use the autobuffered transmit mode of operation with alternate framing. this provides a means for transmitting an entire block of serial data before an interrupt is generated. 07139-029 adsp-21xx adf4360-x sclk sdata le ce muxout (lock detect) sclock mosi tfs i/o ports figure 32. adsp-21xx to adf4360-x interface set up the word length for 8 bits and use three memory locations for each 24-bit word. to program each 24-bit latch, store the 8-bit bytes, enable the autobuffered mode, and write to the transmit register of the dsp. this last operation initiates the autobuffer transfer. pcb design guidelines for chip scale package the leads on the chip scale package (cp-24-2) are rectangular. the pcb pad for these should be 0.1 mm longer than the package lead length and 0.05 mm wider than the package lead width. the lead should be centered on the pad to ensure that the solder joint size is maximized. the bottom of the chip scale package has a central thermal pad. the thermal pad on the pcb should be at least as large as this exposed pad. on the pcb, there should be a clearance of at least 0.25 mm between the thermal pad and the inner edges of the pad pattern to ensure that shorting is avoided. thermal vias can be used on the pcb thermal pad to improve thermal performance of the package. if vias are used, they should be incorporated into the thermal pad at 1.2 mm pitch grid. the via diameter should be between 0.3 mm and 0.33 mm, and the via barrel should be plated with 1 ounce of copper to plug the via. the user should connect the printed circuit thermal pad to agnd. this is internally connected to agnd.
data sheet adf4360-9 rev. b | page 23 of 24 the recommended value of this inductor changes with the vco center frequency. figure 35 shows a graph of the optimum inductor value vs. center frequency. output matching there are a number of ways to match the vco output of the adf4360-9 for optimum operation; the most basic is to use a 51 resistor to v vco . a dc bypass capacitor of 100 pf is connected in series, as shown in figure 33 . because the resistor is not frequency dependent, this provides a good broadband match. the output power in the circuit in figure 33 typically gives ?9 dbm output power into a 50 load. center frequency (mhz) inductance (nh) 300 250 150 200 100 0 50 0 100 200 300 500 400 07139-032 100pf 07139-030 rf out v vco 50? 51 ? figure 33. simple output stage a better solution is to use a shunt inductor (acting as an rf choke) to v vco . this gives a better match and, therefore, more output power. figure 35. optimum shunt inductor vs. center frequency both complementary architectures can be examined using the ev-adf4360-9eb 1 z evaluation board. if the user does not need the differential outputs available on the adf4360-9, the user should either terminate the unused output with the same circuitry as much as possible or combine both outputs using a balun. alternatively, instead of the lc balun, both outputs can be combined using a 180 rat-race coupler. experiments have shown that the circuit shown in figure 34 provides an excellent match to 50 over the operating range of the adf4360-9. this gives approximately 0 dbm output power across the specific frequency range of the adf4360-9 using the recommended shunt inductor, followed by a 100 pf dc-blocking capacitor. l 100pf 07139-031 rf out v vco 50? if the user is only using divout and does not use the rf outputs, it is still necessary to terminate both rf output pins with a shunt inductor/resistor to v vco and also a dc bypass capacitor and a 50 load. the circuit in figure 33 is probably the simplest and most cost-effective solution. it is important that the load on each pin be balanced because an unbalanced load is likely to cause stability problems. terminations should be identical as much as possible. figure 34. optimum output stage
adf4360-9 data sheet rev. b | page 24 of 24 outline dimensions compliant to jedec standards mo-220-vggd-2 08-18-2010-a 1 0.50 bsc p i n 1 i n d i c a t o r 2.50 bcs 0.50 0.40 0.30 top view 12 max 0.70 max 0.65 typ seating plane coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 0.20 min 2.45 2.30 sq 2.15 24 7 19 12 13 18 6 (bottom view) 0.60 max 0.60 max pin 1 indicator 4.10 4.00 sq 3.90 3.75 bsc sq exposed pad for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 36. 24-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-24-2) dimensions shown in millimeters ordering guide model 1 temperature range package description frequency range package option adf4360-9bcpz ?40c to +85c 24-lead lfcsp_vq 65 mhz to 400 mhz cp-24-2 adf4360-9bcpzrl ?40c to +85c 24-lead lfcsp_vq 65 mhz to 400 mhz cp-24-2 adf4360-9bcpzrl7 ?40c to +85c 24-lead lfcsp_vq 65 mhz to 400 mhz cp-24-2 EV-ADF4360-9EB1Z evaluation board 1 z = rohs compliant part. ?2008C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07139-0-2/12(b)

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